During the design of any digital component, tests are required to determine the manufacturability of the component. FIG. 1 illustrates a conventional flow diagram of a typical digital design. Rough sizing and capabilities are created in the Design Concept stage, as represented by blocks 1, 2, and 3, along with some high level data or control flow paths, and some high level interconnections between major functions. During the high level design (HLD) phase, represented by blocks 4, 5, and 6, the design is broken down into its smallest pieces. These design pieces are coded in a design language, for example, Very high speed integrated circuit Hardware Description Language (VHDL). Possible design languages are well known in the art. At this point, the design represents a close approximation of the final design, where the coded pieces do not necessarily achieve the final timing, area, or power budgets, nor do they implement all the necessary functions. During the low level design (LLD) phase, represented by blocks 7, 8, and 9, all levels of logic are implemented. Through successive iterations, the design eventually meets all budgets and performs all functions.
The verification of manufacturability, i.e., that the complete design complies with test structure rules, cannot begin until all low level blocks have been coded, represented in box 6. The impact of block interconnections on manufacturability also cannot be verified until box 6, or perhaps as late as chip completion, represented by box 9. This can cause schedule slippage and/or lower quality manufacturing tests to be developed if problems are found late in the design process.
Accordingly, there exists a need for an improved method and process to verify a digital logic design complies with certain manufacturing test rules or guidelines. The improved method and process should allow verification of manufacturability before all low level logics are implemented. The present invention addresses such a need.